Synchronous interface to a self-timed memory array

ABSTRACT

A synchronous interface to a self-timed memory array includes one or more address bus inputs and a first latch stage that includes one or more latches. Each of the latches of the first latch stage includes an input coupled to one of the address bus inputs and a first output. The synchronous interface further includes a second latch stage that includes a plurality of latches. Each of the latches of the second latch stage includes an input coupled to one of the first outputs of the first latch stage and a second output coupled to the memory array.

FIELD OF THE INVENTION

The present invention is directed to an interface to a memory array.More particularly, the present invention is directed to a synchronousinterface to a self-timed memory array.

BACKGROUND OF THE INVENTION

Many computer devices operate based on an external clock. For example, aprocessor may receive a clock input and perform all operations or eventsonly when the clock transitions. Devices in which events proceed basedon a clock transition are referred to as "synchronous" devices.

Other computer devices do not base their operation on an external clock.These devices are referred to as "asynchronous" or "self-timed" devices.A memory array such as that contained in a cache subsystem is oneexample of a device that can be implemented as a self-timed device. Aself-timed memory array typically receives a request from a processor(e.g., a read or write request). The memory array then performs theoperation and indicates to the processor when the operation is complete.However, the time required for the operation to complete is not based onan external clock (i.e., a predetermined number of clock cycles).Rather, in the case of a self-timed cache subsystem, the time requiredis based on the asynchronous delay paths through the device, which mayvary in duration based on the operations that are performed.

Self-timed devices typically have some performance advantages oversynchronous devices. Specifically, self-timed devices have a lower speedpower product than similar synchronous devices. A speed power product isthe speed of the device multiplied by the power consumed by the deviceat a given frequency. With self-timed devices, power is only consumedduring operations. In contrast, with synchronous devices, power isconsumed by clock distribution buffers even when operations are notbeing performed.

Synchronous devices frequently are required to interact with self-timeddevices. When a synchronous device interacts with self-timed memoryarrays, there is a need for an input interface that receives inputsignals from the synchronous device.

Specifically, the device containing the self-timed memory array needs toaccept input signals using the clock-based protocol of the synchronousdevice. For example, a synchronous device will typically drive validdata for a window of time around a clock edge or edges as defined bysetup time (i.e., a valid time before a clock edge) and hold time (i.e.,a valid time after a clock edge) specifications. The self-timed device,however, may need input data for a duration of time that is different(e.g., longer) than the synchronous time provides. Thus, a synchronousinterface is needed to convert the input signals to a protocol that iscompatible with the self-timed memory array timing requirements.

The interface must make the self-timed memory array appear to be asynchronous device to other devices. For maximum performance, theinterface should also reduce input/output signal delay, and minimize theinput signal setup time and hold time requirements.

Based on the foregoing, there is a need for such a synchronous interfaceto a self-timed memory array.

SUMMARY OF THE INVENTION

One embodiment of the present invention is a synchronous interface to aself-timed memory array. The synchronous interface includes one or moreaddress bus inputs and a first latch stage that includes one or morelatches. Each of the latches of the first latch stage includes an inputcoupled to one of the address bus inputs and a first output. Thesynchronous interface further includes a second latch stage thatincludes a plurality of latches. Each of the latches of the second latchstage includes an input coupled to one of the first outputs of the firstlatch stage and a second output coupled to the memory array.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram partially illustrating one embodiment of acomputer system that implements the present invention.

FIG. 2 is a circuit diagram of a synchronous interface in accordancewith one embodiment of the present invention.

FIGS. 3a and 3b are block and circuit diagrams, respectively, of oneembodiment of a pulsed transparent latch.

FIGS. 4a and 4b are block and circuit diagrams, respectively, of oneembodiment of a pulsed set latch.

FIG. 5 is a timing diagram illustrating the operation of the synchronousinterface at a low frequency.

FIG. 6 is a timing diagram illustrating the operation of the synchronousinterface at a moderate frequency.

FIG. 7 is a timing diagram illustrating the operation of the synchronousinterface at a high frequency.

DETAILED DESCRIPTION

FIG. 1 is a block diagram partially illustrating one embodiment of acomputer system that implements the present invention. The computersystem 10 includes a central processing unit ("CPU") 12 and a cachesubsystem 30 which is comprised of multiple memory arrays (e.g., a cachememory array and a tag memory array). CPU 12 is coupled to cachesubsystem 30 through an address bus 34, an address strobe 36 and a databus 18. Computer system 10 further includes a clock 16 which provides aclock signal to CPU 12 and cache subsystem 30.

Cache subsystem 30 includes a tag memory 14 and a plurality of cachememory 20-23. In one embodiment, cache memory 20-23 is comprised of aplurality of rows of high-speed static random access memory ("SRAM").Cache memory 20-23 stores memory blocks from the main memory (not shownin FIG. 1) of computer system 10. CPU 12 can access the memory blocksstored in cache memory 20-23 more quickly than memory blocks stored inthe main memory.

Each memory block stored in cache memory 20-23 is assigned a uniqueidentifier, referred to as a "tag." Tags memory 14 stores the tags foreach cached memory block. CPU 12 requests access to a cached memoryblock via address bus 34 and address strobe 36. Address strobe 36indicates when a valid address is on address bus 34.

Tag memory 14 receives a request for a memory block from CPU 12. Therequest includes a memory address on address bus 34 and a valid addresssignal on address strobe 36. Tag memory 14 decodes the memory address,and determines whether the requested memory block is stored in cachememory 20-23. If so, the requested memory block is selected from cachememory 20-23 via select line 24. The selected memory block is thentransferred to CPU 12 from cache memory 20-23 via data bus 18. Tagmemory 14 generates an "end operation" signal when a self-timed cacheoperation is complete and cache subsystem 30 is able to accept anotherrequest from CPU 12.

CPU 12 is a synchronous device because all of its operations are basedon clock 16. In contrast, cache subsystem 30 is a self-timed devicebecause each cache operation requires a variable amount of time that isnot synchronized with clock 16. Therefore, cache subsystem 30 includes asynchronous interface 32. Synchronous interface 32 allows cachesubsystem 30 to appear to be a synchronous device to CPU 12.

FIG. 2 is a circuit diagram of synchronous interface 32 coupled to thetag memory array 70 of cache subsystem 30. Synchronous interface 32receives address bus 34 and address strobe 36 as inputs from CPU 12. Inthe embodiment of FIG. 2, address bus 34 is a three-bit address bus.However, in other embodiments, address bus 34 can comprise any number ofbits. Address bus 34 is received on input pads 100-102. Address strobe36 is received on ADS input pad 103. Clock 16 is received on CLK inputpad 104. Each input pad 100-104 is coupled to an input buffer 40-44,respectively.

CLK input buffer 44 is coupled to a setup and hold time adjustment delaycircuit 74. Setup and hold time adjustment delay circuit 74 adjusts thesetup and hold time of synchronous interface 32. An inverter 81 iscoupled to delay circuit 74 and outputs "ck# signal" on a line 76. Ck#signal is a delayed inverse signal of clock 16. An inverter 82 iscoupled to inverter 81 and outputs "ck signal" on line 78. Ck signal isa delayed signal of CLK 104.

Synchronous interface 32 includes a plurality of transparent latches50-52 and 56. In one embodiment, transparent latches 50-52 and 56 areD-type latches or flip-flops. ADS input buffer 43 is coupled to aD-input of transparent latch 56. The enable input of transparent latch56 is coupled to line 76 (ck# signal).

Synchronous interface 32 further includes a plurality of pulsed latches60-65. In one embodiment, pulsed latches 60-65 are "pulsed transparent"latches. In another embodiment, pulsed latches 60-65 are "pulsed set"latches. FIGS. 3a and 3b are block and circuit diagrams, respectively,of one embodiment of a pulsed transparent latch which can be used forpulsed latches 60-65 of FIG. 2.

Pulsed transparent latch 110 of FIG. 3a includes a D-type transparentlatch 100. D-type latch 100 includes a D-input, a Q-output, a resetinput 105 and an enable input 106. Pulsed latch 110 further includes adual input AND gate 102 and a rising edge detector 104. The output ofAND gate 102 is coupled to enable input 106. A rising edge signal iscoupled to the input of rising edge detector 104. The output of risingedge detector 104 is coupled to one input of AND gate 102 and an enablesignal is coupled to the other input of AND gate 102. In operation, theD-input of latch 100 is output at the Q-output on the rising edge of therising edge signal when the enable signal is high.

Pulsed transparent latch 120 of FIG. 3b is implemented with a pluralityof inverters 121-128, NAND gates 130 and 131, NOR gate 132, and passgates 133 and 134. Pass gates 133 and 134 each comprise a pair oftransistors.

Referring again to FIG. 2, synchronous interface 32 further includes apulsed latch 66. In one embodiment, pulsed latch 66 is a "pulsed set"latch. FIGS. 4a and 4b are block and circuit diagrams, respectively, ofone embodiment of a pulsed set latch which can be used for pulsed latch66 of FIG. 2 and can be used for pulsed latches 60-65 of FIG. 2.

Pulsed set latch 150 of FIG. 4a includes a set/reset latch 156.Set/reset latch 156 includes an S-input, a Q-output and a reset input.Pulsed set latch 150 further includes a triple input AND gate 154 and arising edge detector 151. The output of AND gate 154 is coupled to theS-input of latch 156. A rising edge signal is coupled to the input ofrising edge detector 151. The output of rising edge detector 151 iscoupled to one input of AND gate 154, and an enable signal and anS-input signal is coupled to the other inputs of AND gate 154. Inoperation, the rising edge of the rising edge signal is output at theQ-output of latch 156 when the S-input signal and the enable signal arehigh.

Pulsed set latch 160 of FIG. 4b is implemented with a plurality ofinverters 161-168, a NAND gate 170 and a NOR gate 171. Pulsed set latch160 further includes a plurality of transistors 172-174.

Referring again to FIG. 2, the Q-output of transparent latch 56 iscoupled to an S-input of pulsed latch 66. The pulsed input of pulsedlatch 66 is coupled to line 78 (ck signal). The Q-output of latch 66 isreceived by tag memory array 70 as an address strobe. End operation line72 from tag memory array 70 is coupled to the reset input of latch 66.

Address bus 34 bits received from address bus pads 100-102 pass throughtwo stages of latches. The first stage of latches, latch stage 80,includes the plurality of transparent latches 50-52 corresponding toeach input buffer 40-42. The outputs of input buffers 40-42 are coupledto the D-inputs of latches 50-52, respectively. Line 76 (ck# signal) iscoupled to the enable inputs of latches 50-52.

In operation, latch stage 80 is controlled by the ck# signal only.Therefore, the setup and hold time of address bus inputs 100-102 aredependent only on clock 16. This satisfies the timing requirements ofsynchronous interface 32. The setup and hold times of input signalsreceived by synchronous interface 32 can be minimized because they areindependent of address strobe 36.

The second stage of latches, latch stage 82, includes latches 60-65.Line 78 (ck signal) is coupled to the pulsed inputs of latches 60-65.The Q-output of latch 56 is coupled to the enable input of latches60-65. End operation line 72 from memory array 70 is coupled to thereset inputs of latches 60-65.

Each latch 50-52 of latch stage 80 has a corresponding pair of latches60-65 in latch stage 82. The respective Q-outputs of latches 50-52 andtheir inverse are coupled to the D-inputs of the respective latches oflatch stage 82 (or the S-inputs if latches 60-65 are pulsed setlatches). For example, the Q-output of latch 50 is coupled to theD-input of latch 60 and the inverse of the Q-output of latch 50 iscoupled to the D-input of latch 61.

In operation, latches 60-65 of latch stage 82 are strobed on by addressstrobe 36 and the rising edge of the ck signal. Further, latches 60-65are reset asynchronously when access to tag memory array 70 is complete,as indicated by end operation line 72. This satisfies the self-timedrequirement of synchronous interface 32.

The two stages of latches, latch stages 80 and 82, work in combinationto capture and hold data from address bus 34 for the duration of timerequired for tag memory array 70. Transparent latches 50-52 of latchstage 80 act as master latches and are enabled by the ck# signal. Pulsedlatches 60-65 of latch stage 82 act as slave-latches to capture addressdata on the rising edge of the ck signal when enabled by the output oflatch 56.

In synchronous interface 32, address strobe 36 is sampled by tag memoryarray 70 on the rising edge of clock 16. In contrast, address bus 34 issampled by memory array 70 on the rising edge of clock 16 if and only ifaddress strobe 36 is asserted. Tag memory array 70 is self-timed andwill perform an access (i.e., read or write) asynchronously relative toclock 16.

Tag memory array 70 is allowed two or more clock 16 periods to completean access before another access is permitted. The number of clock 16periods allowed for a given array access is determined by the spacingbetween strobes on address strobe 36. For example, at a low clock 16frequency, the minimum spacing of the strobes on address strobe 36 maybe set to two clock 16 cycles. However, at higher clock 16 frequencies,the minimum spacing of the strobes on address strobe 36 may be set tothree or more clock 16 cycles to accommodate the same tag memory array70 access.

Synchronous interface 32 provides many advantages. For example, someprior art synchronous interfaces require extra circuitry to insurealternate minimum clock cycle spacings between address strobe signals.However, in synchronous interface 32, latch stage 82 is not updateduntil the next strobe on address strobe 36 occurs, regardless of thestrobe spacing on address strobe 36. Further, synchronous interface 32minimizes address bus 34 setup and hold windows. In synchronousinterface 32, setup and hold requirements are relative only to latchstage 80 and are dependent only on the path from CLK 104 to the ck#signal.

Synchronous interface 32 can also be used to interface additionalsignals received in conjunction with address strobe 36. For example, acommand signal on a command bus that is sent along with address strobe36 can be interfaced using two stage of latches in the same manner asthe address bus 34 signals

FIG. 5 is a timing diagram illustrating the operation of synchronousinterface 32 at a low frequency. As shown, the pulse enable ck 78 signalcaptures the address data and address strobe on latch stage 82. Theaddress data and address strobe are held until end operation 72 signalis received. If latch stage 82 was not pulsed enabled, then the enableinput of latch stage 82 would be in contention with the end operation 72reset signal when synchronous interface 32 is operated at low frequency.

FIG. 6 is a timing diagram illustrating the operation of synchronousinterface 32 at a moderate frequency. FIG. 6 illustrates that the valueof address bus 34 only matters when address strobe 36 is high during therising edge of clock 16 (note the "no operation" of address strobe 36during the second rising edge of clock 16 and the effect on the latchstage 80 address).

FIG. 7 is a timing diagram illustrating the operation of synchronousinterface 32 at a high frequency. As shown in FIG. 7, the duration ofaccess to tag memory array 70 can span multiple clock 16 cycles at ahigh frequency.

Several embodiments of the present invention are specificallyillustrated and/or described herein. However, it will be appreciatedthat modifications and variations of the present invention are coveredby the above teachings and within the purview of the appended claimswithout departing from the spirit and intended scope of the invention.

For example, although the embodiments disclosed provide a synchronousinterface to a tag memory array, the present invention can beimplemented as an interface to any type of self-timed device.

What is claimed is:
 1. A synchronous interface to a self-timed memoryarray which outputs an end operation signal, said interfacecomprising:one or more address bus inputs; a clock input: a first latchstage including one or more first latches, each of said first latchesincluding an input coupled to one of said address bus inputs, an enableinput coupled to said clock input and a first output; an address strobeinput; and a second latch stage including a plurality of second latches,each of said second latches including an input coupled to one of saidfirst outputs, an enable input coupled to said address strobe input, arising edge input coupled to said clock input and a reset input coupledto the end operation signal and a second output coupled to said memoryarray.
 2. The synchronous interface of claim 1, wherein said firstlatches are transparent latches.
 3. The synchronous interface of claim1, wherein said second latches are pulsed latches.
 4. The synchronousinterface of claim 3, wherein said second latches are pulsed transparentlatches.
 5. The synchronous interface of claim 3, wherein said secondlatches are pulsed set latches.
 6. The synchronous interface of claim 3,wherein said pulsed latches comprise:a D-type flip-flop having a resetinput and an enable input; an AND gate having an input and having anoutput coupled to said enable input; and a rising edge detector coupledto said AND gate input.
 7. The synchronous interface of claim 1, whereinthe memory array is a cache subsystem.
 8. The synchronous interface ofclaim 1, wherein said clock input is coupled to an adjustment delaycircuit.
 9. The synchronous interface of claim 1, wherein each of saidfirst output is coupled to an inverter having an output, and saidinverter output is coupled to one of said second latches input.
 10. Thesynchronous interface of claim 1, further comprising a third latch, saidthird latch including an input coupled to said address strobe input, anenable input coupled to said clock input and an output coupled to saidenable inputs of each of said second latches, wherein said third latchis a transparent latch.
 11. A computer system comprising:an address busincluding one or more address bus bits; a central processing unitcoupled to said address bus; and a memory subsystem including asynchronous interface and a memory array, wherein said synchronousinterface comprises:a clock input; a first latch stage including one ormore first latches, each of said first latches including an inputcoupled to one of said address bus bits, an enable input coupled to saidclock input and a first output; an address strobe input; and a secondlatch stage including a plurality of second latches, each of said secondlatches including an input coupled to one of said first outputs, anenable input coupled to said address strobe input, a rising edge inputcoupled to said clock input and a reset input coupled to the endoperation signal and a second output coupled to said memory array. 12.The computer system of claim 11, wherein said first latches aretransparent latches.
 13. The computer system of claim 11, wherein saidsecond latches are pulsed latches.
 14. The computer system of claim 13,wherein said memory array is a cache subsystem.
 15. The computer systemof claim 13, wherein said clock input is coupled to an adjustment delaycircuit.
 16. The computer system of claim 13, wherein each of said firstoutput is coupled to an inverter having an output, and said inverteroutput is coupled to one of said second latches input.
 17. The computersystem of claim 11, wherein said synchronous interface further comprisesa third latch, said third latch including an input coupled to saidaddress strobe input, an enable input coupled to said clock input and anoutput coupled to said enable inputs of each of said second latches. 18.The computer system of claim 13, wherein said central processing unit isa synchronous device and said memory array is a self-timed device.
 19. Amethod of interfacing a self-timed memory array to a plurality ofaddress bus signals, a clock signal and an address strobe signal, saidmethod comprising the steps of:inputting the address bus signals to afirst latch stage having an output, wherein the first latch stage isenabled by the clock signal; inputting the output of the first latchstage to a second latch stage having an output, wherein the second latchstage is enabled by the address strobe signal and pulsed by the clocksignal; and providing the output of the second latch stage to the memoryarray.
 20. The method of claim 19, further comprising the stepsof:receiving an end operation signal from the memory array; andresetting the second latch stage based on the end operation signal. 21.The method of claim 19, wherein the first latch stage comprises one ormore transparent latches.
 22. The method of claim 19, wherein the secondlatch stage comprises a plurality of pulsed latches.
 23. The method ofclaim 20, further comprising the step of:delaying the clock signal toadjust a setup and hold time.